1. Field of the Invention
The present invention concerns a D-type master-slave flip-flop, advantageously one implemented in the CMOS technology.
2. Description of the Prior Art
A master-slave flip-flop of the above kind is described in "Analyse et synthese des systemes logiques" ["Analysis and synthesis of logic systems"], by D. Mange, Vol. V of "Traite d'electricite" ["Treatise on electricity"], Ecole Polytechnique Federale de Lausanne, Switzerland, published by Editions Georgi, 1978, page 260.
As shown in FIG. 1 on the accompanying drawings, the prior art master-slave flip-flop includes a master unit MA receiving an input variable D and producing two first intermediate variables M and NM, both of which are a function of the input variable. The master-slave flip-flop also includes a slave unit E adapted to form at least one output variable Q and/or NQ of the flip-flop from said first intermediate variables M and NM. A transfer unit T connected between the master unit MA and the slave unit E respectively includes, for each of said output variables Q and NQ, at least one logic gate P1 and P2 adapted to combine the first intermediate variables N and NM applied to it with a clock signal CK, producing two second intermediate variables X and Y which are applied to the slave unit E.
In the prior art embodiment shown, the master unit MA comprises two NAND gates P3 and P4 and the slave unit E comprises two NAND gates P5 and P6.
The essential advantages of this type of prior art flip-flop are that they have no race (critical travel) and do not need a clock inverter. Also, the clock signal is applied only to gates P1 and P2 of the transfer unit T. See document EP 0 734 122 for a detailed explanation of the "race" concept (which is well known in the art).
However, these flip-flops have a drawback due to their sensitivity to the slope of the rising or falling edge of the pulses of the clock signal CK.
FIGS. 2 and 3 of the appended drawings show the consequences of this sensitivity of the flip-flop to the slope of the clock signal. FIG. 2 shows that, if the clock signal CK changes state, for example from "1" to "0", the variable X goes from "0" to "1" and the variable M goes from "1" to "0". Considering the variable Y during this same process, it can be seen that the rise in the variable X creates an uncertainty or glitch in the variable Y if the clock signal is relatively slow to reach its low level.
FIG. 3 shows this phenomenon by means of a model of the transfer unit T whose gate P2 receives the clock signal CK subject to a time-delay Dl of duration .delta.w and whose gate P1 supplies the variable X subject to a time-delay D2 of duration .delta.x. There is a glitch in the variable Y if .delta.w&gt;.delta.x, which can result from an erroneous change of state of the slave unit E in response to a 1.fwdarw.0.fwdarw.1 glitch in the variable Y.
The object of the invention is to provide a D-type master-slave flip-flop in which the influence of the slope of the flanks of the clock signal pulse is greatly reduced, if not completely eliminated.